In the computing business, we’ve lived with PCIe as a typical for a very long time. It is used so as to add any extra options to a system: graphics, storage, USB ports, extra storage, networking, add-in playing cards, storage, sound playing cards, Wi-Fi, oh did I point out storage? Well the one factor that we haven’t been capable of put right into a PCIe slot is DRAM – I don’t imply DRAM as a storage gadget, however reminiscence that really is added to the system as useable DRAM. Back in 2019 a brand new CXL normal was launched, which makes use of a PCIe 5.Zero hyperlink because the bodily interface. Part of that normal is CXL.reminiscence – the flexibility so as to add DRAM right into a system by means of a CXL/PCIe slot. Today Samsung is unveiling the primary DRAM module particularly designed on this means.
CXL: A Refresher
The unique CXL normal began off as a analysis venture inside Intel to create an interface that may help accelerators, IO, cache, and reminiscence. It subsequently spun out into its personal consortium, with over 50+ members, and help from key gamers within the business: Intel, AMD, Arm, IBM, Broadcom, Marvell, NVIDIA, Samsung, SK Hynix, WD, and others. The newest normal is CXL 2.0, finalized in November 2020.
The CXL 1.1 normal covers three units of intrinsics, generally known as CXL.io, CXL.reminiscence and CXL.cache. These enable for deeper management over the linked gadgets, in addition to an enlargement as to what’s doable. The CXL consortium sees three fundamental areas for this:
The first kind is a cache/accelerator, similar to an offload engine or a SmartNIC (a wise community controller). With the CXL.io and CXL.cache intrinsics, this is able to enable the community controller to type incoming information, analyze it, and filter what is required straight into the primary processors reminiscence.
The second kind is an accelerator with reminiscence, and direct entry to the HBM on the accelerator from the processor (in addition to entry to DRAM from the accelerator). The thought is a pseudo-heterogeneous compute design permitting for less complicated however dense computational solvers.
The third kind is maybe the one we’re most eager about right this moment: reminiscence buffers. Using CXL.reminiscence, a reminiscence buffer could be put in over a CXL hyperlink and the hooked up reminiscence could be straight pooled with the system reminiscence. This permits for both elevated reminiscence bandwidth, or elevated reminiscence enlargement, to the order of 1000’s of gigabytes.
CXL 2.Zero additionally introduces CXL.safety, help for persistent reminiscence, and switching capabilities.
It must be famous that CXL is utilizing the identical electrical interface as PCIe. That means any CXL gadget may have what seems like a PCIe bodily connector. Beyond that, CXL makes use of PCIe in its startup course of, so at the moment any CXL supporting gadget has to additionally help a PCIe-to-PCIe hyperlink, making any CXL controller additionally a PCIe controller by default.
One of the widespread questions I’ve seen is what would occur if a CXL-only CPU was made? Because CXL and PCIe are intertwined, a CPU can’t be CXL-only, it must help PCIe connections as properly. That being stated, from the opposite course: if we see CXL-based graphics playing cards for instance, they’d additionally need to a minimum of initialize over PCIe, nonetheless full working modes may not be doable if CXL isn’t initialized.
Intel is ready to introduce CXL 1.1 over PCIe 5.Zero with its Sapphire Rapids processors. Microchip has introduced PCIe 5.Zero and CXL-based retimers for motherboard hint extensions. Samsung right this moment is the third announcement for CXL supported gadgets. IBM has an analogous expertise referred to as OMI (OpenCAPI Memory Interface), nonetheless that hasn’t seen large adoption exterior of IBM’s personal processors.
Samsung’s CXL Memory Module
Modern processors depend on reminiscence controllers for hooked up DRAM entry. The high line x86 processors have eight channels of DDR4, whereas a lot of…
