When it involves particulars of the SoC, it’s referred to as Rhea and it is going to be a 72-core Arm ISA primarily based processor with Neoverse Zeus cores interconnected by a mesh. There are going to be 68 mesh community L3 cache slices in between all the cores. All of that shall be manufactured utilizing TSMC’s 6 nm excessive ultraviolet lithography (EUV) expertise for silicon manufacturing. The Rhea SoC design will make the most of 2.5D packaging with many IP blocks stitched collectively and HBM2E reminiscence current on the die. It is unknown precisely what configuration of HBM2E goes to be current. The system will even see assist for DDR5 reminiscence and thus allow two-level system reminiscence by combining HBM and DDR. We are excited to see how the ultimate product appears to be like like and now we look forward to extra updates on the mission.