When JEDEC launched its DDR5 specification (JESD79) again in 2020, the usual setting group outlined exact specs for modules with velocity bins of as much as 6400 MT/s, whereas leaving the spec open to additional expansions with quicker reminiscence as know-how progressed. Now, a bit greater than three-and-a-half years later, and the requirements physique and its members are gearing as much as launch a quicker era of DDR5 reminiscence, which is being specified by the newly up to date JESD79-JC5 specification. The newest iteration of the DDR5 spec defines official DDR timing specs as much as 8800 MT/s, in addition to including some new options with regards to safety.
Diving in, the brand new specification outlines settings for reminiscence chips (on all sorts of reminiscence modules) with information switch charges as much as 8800 MT/s (AKA DDR5-8800). This suggests that every one members of the JESD79 committee that units the specs for DDR5 — together with reminiscence chip makers and reminiscence controller designers — agree that DDR5-8800 is a viable extension of the DDR5 specification each from efficiency and price standpoint. Meanwhile, the addition of upper velocity bins is maybe enabled by one other JEDEC characteristic launched on this newest specification, which is the Self-Refresh Exit Clock Sync for I/O coaching optimization.
| JEDEC DDR5-A Specifications | |||||||
| AnandTech | Data Rate MT/s |
CAS Latency (cycles) | Absolute Latency (ns) | Peak BW GB/s |
|||
| DDR5-3200 | A | 3200 | 22 | 22 | 22 | 13.75 | 25.6 |
| DDR5-3600 | A | 3600 | 26 | 26 | 26 | 14.44 | 28.8 |
| DDR5-4000 | A | 4000 | 28 | 28 | 28 | 14 | 32 |
| DDR5-4400 | A | 4400 | 32 | 32 | 32 | 14.55 | 35.2 |
| DDR5-4800 | A | 4800 | 34 | 34 | 34 | 14.17 | 38.4 |
| DDR5-5200 | A | 5200 | 38 | 38 | 38 | 14.62 | 41.6 |
| DDR5-5600 | A | 5600 | 40 | 40 | 40 | 14.29 | 44.8 |
| DDR5-6000 | A | 6000 | 42 | 42 | 42 | 14 | 48 |
| DDR5-6400 | A | 6400 | 46 | 46 | 46 | 14.38 | 51.2 |
| DDR5-6800 | A | 6800 | 48 | 48 | 48 | 14.12 | 54.4 |
| DDR5-7200 | A | 7200 | 52 | 52 | 52 | 14.44 | 57.6 |
| DDR5-7600 | A | 7600 | 54 | 54 | 54 | 14.21 | 60.8 |
| DDR5-8000 | A | 8000 | 56 | 56 | 56 | 14 | 64.0 |
| DDR5-8400 | A | 8400 | 60 | 60 | 60 | 14.29 | 67.2 |
| DDR5-8800 | A | 8800 | 62 | 62 | 62 | 14.09 | 70.4 |
When it involves the JEDEC customary for DDR5-8800, it units comparatively free timings of CL62 62-62 for A-grade gadgets and CL78 77-77 for lower-end C-grade ICs. Unfortunately, the legal guidelines of physics driving DRAM cells haven’t improved a lot during the last couple of years (or many years, for that matter), so reminiscence chips nonetheless should function with comparable absolute latencies, driving up the relative CAS latency. In this case 14ns stays the gold customary, with CAS latencies on the new speeds being set to carry absolute latencies round that mark. But in change for programs keen to attend a bit longer (when it comes to cycles) for a outcome, the brand new spec improves the usual’s peak reminiscence bandwidth by 37.5%.
This in fact is simply the timings set within the JEDEC specification, which is primarily of concern for server distributors. So we’ll need to see simply how a lot more durable client reminiscence producers can push issues for his or her XMP/EXPO-profiled reminiscence. Extreme overclockers are already hitting speeds as excessive as 11,240 MT/s with current-generation DRAM chips and CPUs, so there could also be some extra headroom to play with within the subsequent era.
Meanwhile, on the safety entrance, the up to date spec makes a few modifications which have been put in place seemingly to deal with rowhammer-style exploits. The massive merchandise right here is Per-Row Activation Counting (PRAC), which true to…
