Like most company communications, how corporations discuss themselves must be taken with a few kilos of salt. The worst are usually simplistically self-aggrandizing. Yet different examples can provide significant insights into a company’s plans and self-perception.
That is especially true following vital adjustments in management, such because the January announcement that Pat Gelsinger (then CEO of VMware) would substitute Bob Swan as Intel’s CEO. On July 26 on the “Intel Accelerated” occasion, Gelsinger, Dr. Ann Kelleher, SVP and GM of Intel Technology Development and different firm executives revealed a roadmap for brand new merchandise that will likely be delivered by way of 2025 and past. What Pat Gelsinger and his workforce mentioned is actually price contemplating, however how they talked about additionally it is intriguing.
Meaty improvements
The detailing of Intel’s new course of and packaging improvements started with a daring disclaimer by Gelsinger. “The industry has long recognized that traditional nanometer-based process node naming stopped matching the actual gate-length metric in 1997.” In different phrases, the nanometer (or “nm”) associated advertising and marketing phrases and rhetoric that silicon producers have trusted for 20+ years has reached the top of its helpful life because it doesn’t meaningfully replicate or describe semiconductor efficiency.
To handle that, Gelsinger mentioned Intel will make use of 5 new node names and related improvements for Core and Xeon merchandise launched by way of 2025 and past. Intel 7, Intel 4, and Intel three will leverage current FinFet transistor optimizations and subsequent gen excessive ultraviolet (EUV) manufacturing instruments, leading to a close to 50% improve in efficiency per watt between now and 2H 2023.
Intel can also be engaged on subsequent gen EUV; Numerical High Aperture (High NA) EUV that will likely be utilized in future merchandise. Those embrace Intel 20A which is deliberate to ramp in 2024 as the corporate enters what Gelsinger referred to as the “angstrom era” of semiconductor manufacturing with RibbonFET, its first new transistor structure since 2011.
RibbonFET is designed to ship markedly quicker switching speeds with the identical drive present as a number of fins however in a smaller footprint. The new chips may also incorporate one other Intel innovation; PowerVia, a bottom energy supply know-how that optimizes sign transmission by eliminating energy routing on the entrance aspect of the wafer. Intel 18A (scheduled for 2025) will use the identical applied sciences to ship one other vital efficiency enhance.
Packaging and companion potatoes
Packaging is an more and more necessary situation for Intel, particularly contemplating the IDM 2.zero technique that marks a major effort by the corporate to promote Intel Foundry Services (IFS) choices to “fabless” semiconductor clients. IFS is a brand new standalone foundry enterprise led by Dr. Randhir Thakur, who will report on to Gelsinger. At Intel Accelerated, Gelsinger famous that AWS has signed on to grow to be IFS’s first buyer.
On the packaging aspect, Intel will proceed to leverage the EMIB (embedded multi-die interconnect bridge) 2.5D embedded bridge options it launched in 2017 and Foveros, a wafer-level packaging functionality that allows 3D wafer stacking. Intel additionally introduced Foveros Omni, a extremely versatile subsequent gen know-how that will likely be prepared for quantity manufacturing in 2023, and Foveros Direct (additionally out there in 2023) which enhances Foveros Omni by enabling an order of magnitude improve in interconnect density.
Along with its course of and packaging improvements, Intel highlighted notable new future-focused collaborations, together with strategic partnerships with ASML on the event of High NA FUV, and with Qualcomm which…
