AMD today took a significant step into the server and datacenter market and is releasing some info on their upcoming high-performance CPU for servers, codenamed “Naples”. This is going to be a real game-changer in that segment of the market as it does everything Intel does, but better and with more of everything.
Designed to disrupt the status-quo and to scale across the cloud datacenter and traditional on-premise server configurations, “Naples” delivers the highly regarded “Zen” x86 processing engine in industry-leading configurations of up to 32 cores. These 32-core processors can handle 64 threads. Basically Naples is a two-socket server chip pitted against Intel’s Broadwell-EP-based Xeon E5 V4 range. AMD’s chip is “have more of everything.” Naples has 32 cores and is capable of 64 simultaneous threads, eight memory channels, supporting up to 2TB RAM per CPU and 128 PCIe 3.0 lanes.
These setups will get eight memory channels, and everything can be doubled up on a compatible server motherboard. That’s 64-cores SMT and 128 threads with up-to 16-channels of memory. That memory can run 2400/2677 MHz per channel. The memory controller is also capable of using bigger than 16GB DIMMs and in total you could fit 4 TB of DDR4 memory. The Naples processor (well SoC) connects to whatever you need it through over a 128 high-speed I/O-lanes mostly Gen 3. This means you could connect 4 GPU’s, 12 NVMe-SSD’s and some fast 10 GigE Ethernet ports to go along with it. When you couple two processors in SMT, the IO is shared though and 64 lanes will be used for the interconnect in-between the two Naples processors. Each Naples processor has four Zen based 8-core dies interconnected.
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Superior memory bandwidth and the number of high-speed input / output channels in a single-chip further differentiate “Naples” from anything else in the server market today. The first processors are scheduled to be available in Q2 2017, with volume availability building in the second half of the year through OEM and channel partners.
“Today marks the first major milestone in AMD re-asserting its position as an innovator in the datacenter and returning choice to customers in high-performance server CPUs,” said Forrest Norrod, senior vice president and general manager, Enterprise, Embedded and Semi-Custom business unit, AMD. “‘Naples’ represents a completely new approach to supporting the massive processing requirements of the modern datacenter. This groundbreaking system-on-chip delivers the unique high-performance features required to address highly virtualized environments, massive data sets and new, emerging workloads.”
The new AMD server processor exceeds today’s top competitive offering on critical parameters, with 45% more cores1, 60% more input / output capacity (I/O)2, and 122% more memory bandwidth3.
“It is exciting to see AMD back in the server conversation with a new CPU and a sound strategy for why it is the right processor for the modern datacenter and the cloud computing era,” said Matt Eastwood, senior vice president, Enterprise Infrastructure and Datacenter, IDC. “Looking at the product details announced today, it sounds like a compelling combination that will give IT buyers a unique new option to consider when making their next upgrade.”
“Naples” features:
- A highly scalable, 32-core System on Chip (SoC) design, with support for two high-performance threads per core
- Industry-leading memory bandwidth, with 8-channels of memory per “Naples” device. In a 2-socket server, support for up to 32 DIMMS of DDR4 on 16 memory channels, delivering up to 4 terabytes of total memory capacity.
- The processor is a complete SoC with fully integrated, high-speed I/O supporting 128 lanes of PCIe 34, negating the need for a separate chip-set
- A highly-optimized cache structure for high-performance, energy efficient compute
- AMD Infinity Fabric coherent interconnect for two “Naples” CPUs in a 2-socket system
- Dedicated security hardware
AMD will deliver two presentations on its datacenter strategy and upcoming products this week during the Open Compute Summit.
