TSMC this week unveiled its new 6 nm (CLN6FF, N6) manufacturing know-how, which is about to ship a significantly greater transistor density when in comparison with the corporate’s 7 nm (CLN7FF, N7) fabrication course of. An evolution of TSMC’s 7nm node, N6 will proceed to make use of the identical design guidelines, making it simpler for corporations to get began on the brand new course of. The know-how can be used for danger manufacturing of chips beginning Q1 2020.
TSMC states that their N6 fabrication know-how provides 18% greater logic density when in comparison with the corporate’s N7 course of (1st Gen 7 nm, DUV-only), but provides the identical efficiency and energy consumption. Furthermore, in accordance with TSMC N6 ‘leverages new capabilities in excessive ultraviolet lithography (EUVL)’ gained from N7+, however doesn’t disclose how precisely it makes use of EUV for the actual know-how. Meanwhile, N6 makes use of the identical design guidelines as N7 and allows builders of chips to re-use the identical design ecosystem (e.g., instruments, and so on.), which is able to allow them to decrease improvement prices. Essentially, N6 permits to shrink die sizes of designs developed utilizing N7 design guidelines by round 15% whereas utilizing the acquainted IP for extra value financial savings.
| Advertised PPA Improvements of New Process Technologies Data introduced by corporations throughout convention calls, press briefings and in press releases |
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| TSMC | |||||||||
| 16FF+ vs 20SOC |
10FF vs 16FF+ |
7FF vs 16FF+ |
7FF vs 10FF |
7FF+ vs 7FF |
6FF vs 7FF |
5FF vs 7FF |
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| Power | 60% | 40% | 60% | <40% | 10% | ? | 20% | ||
| Performance | 40% | 20% | 30% | ? | identical (?) | ? | 15% | ||
| Area Reduction | none | >50% | 70% | >37% | ~17% | ~15% | 45% | ||
TSMC says that it expects N6 for use for quite a lot of functions, together with cell SoCs, GPUs, high-performance computing chips, networking, 5G infrastructure, and different merchandise. What stays to be seen is whether or not chip designers will be predisposed to make use of N6 know-how given its miniscule enhancements over N7 in the case of energy, efficiency, and space (PPA). Perhaps, corporations with advanced N7-based chips will favor to go on to N7+, and even 5 nm (CLN5FF, N5), for his or her subsequent technology elements.
TSMC will begin danger manufacturing of chips utilizing its N6 fabrication know-how within the first quarter of 2020. Keeping in thoughts that it often takes corporations a few yr to begin high-volume manufacturing (HVM) after the start of danger manufacturing, anticipate N6 for use for mass merchandise ranging from 2021.
Source: TSMC
