While the majority of consideration on TSMC is aimed toward its modern nodes, resembling N3E and N2, a great deal of chips will proceed to be made utilizing extra mature and confirmed course of applied sciences for years to return. Which is why TSMC has continued to refine its current nodes, together with its current-generation 5nm-class choices. To that finish, at its North American Technology Symposium 2024, the corporate launched a brand new, optimized 5nm-class node: N4C.
TSMC’s N4C course of belongs to the corporate’s 5nm-class household of fab nodes and is a superset of N4P, probably the most superior expertise in that household. In a bid to additional carry down 5nm manufacturing prices, for TSMC is implementing a number of adjustments for N4C, together with rearchitecting their normal cell and SRAM cell, altering some design guidelines, and decreasing the variety of masking layers. As a results of these enhancements, the corporate expects N4C to realize each smaller die sizes in addition to a discount in manufacturing complexity, which in flip will carry die prices down by as much as 8.5%. Furthermore, with the identical wafer-level defect density fee as N4P, N4C stands to supply even larger purposeful yields due to its die space discount.
“So, we are not done with our 5nm and 4nm [technologies],” stated Kevin Zhang, Vice President of Business Development at TSMC. “From N5 to N4, we have achieved 4% density improvement optical shrink, and we continue to enhance the transistor performance. Now we bring in N4C to our 4 nm technology portfolio. N4C allows our customers to reduce their costs by remove some of the masks and to also improve on the original IP design like a standard cell and SRAM to further reduce the overall product level cost of ownership.”
TSMC says that N4C can use the identical design infrastructure as N4P, although it’s unclear whether or not N5 and N4P IP might be re-used for N4C-based chips. Meanwhile, TSMC signifies that it provides numerous choices for chipmakers to seek out the fitting steadiness between value advantages and design effort, so corporations fascinated about adopting a 4nm-class course of applied sciences might nicely undertake N4C.
The improvement of N4C comes as a lot of TSMC’s chip design prospects are getting ready to launch chips primarily based on the corporate’s closing technology of FinFET course of expertise, the 3nm N3 collection. While N3 is predicted to be a profitable household, the excessive prices of N3B have been a difficulty, and the technology is marked by diminishing efficiency and transistor density returns altogether. Consequently, N4C might nicely turn out to be a significant, long-lived node at TSMC, serving as match for purchasers who need to keep on with a less expensive FinFET node.
“This is a very significant enhancement, we are working with our customer, basically to extract more value from their 4 nm investment,” Zhang stated.
TSMC expects to start out quantity manufacturing of N4C chips a while subsequent yr. And with TSMC having produced 5nm-class for almost half a decade at that time, N4C ought to be capable of hit the bottom working by way of quantity and yields.
