As a part of the second leg of TSMC’s spring expertise symposium collection, the corporate supplied an replace on the state of its 3nm-class processes, each present and future. Building on the again of their current-generation N3E course of, the optical shrink of this course of expertise, N3P, is now on observe to enter mass manufacturing within the second half of 2024. Thanks to that shrink, N3P is predicted to supply each elevated efficiency effectivity in addition to elevated transistor density over N3E.
N3E in Production, Yielding Well
With N3E already in quantity manufacturing, TSMC is reporting that they are seeing “great” yields on the second-generation 3nm-class course of observe. According to the corporate, the D0 defect density of N3E is at relative parity with N5, matching the defect charge of the older node for a similar level in its respective lifecycle. This isn’t any small feat, given the extra complexities that include growing one final, ever-finer era of FinFET expertise. So for TSMC’s bleeding-edge clients similar to Apple, who simply launched their M4 SoC, that is permitting them to reap the advantages of the improved course of node comparatively shortly.
“N3E started volume production in the fourth quarter of last year, as planned,” a TSMC govt stated on the occasion. “We have seen great yield performance on customers’ products, so they did go to market as planned.”
TSMC’s N3E node is a relaxed model of N3B, eliminating some EUV layers and utterly avoiding the utilization of EUV double patterning. This makes it a bit cheaper to supply, and in some instances it widens the method window and yields, although it comes at the price of some transistor density.
N3P on Track For Second-Half 2024
Meanwhile, wanting in the direction of the speedy future at TSMC, N3P has completed qualification and its yield efficiency is near N3E, in response to the corporate. Being an optical shrink, the N3P node is about to allow processor builders to both improve efficiency by 4% on the similar leakage or cut back energy consumption by 9% on the similar clocks (beforehand the vary was between 4% ~ 10% relying on design). The new node can also be set to spice up transistor density by 4% for a ‘blended’ chip design, which TSMC defines as a processor consisting of 50% logic, 30% SRAM, and 20% analog circuits.
| Advertised PPA Improvements of New Process Technologies Data introduced throughout convention calls, occasions, press briefings and press releases |
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| TSMC | |||||
| N3 vs N5 |
N3E vs N5 |
N3P vs N3E |
N3X vs N3P |
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| Power | -25-30% | -32% | -5% ~ 10% | larger | |
| Performance | +10-15% | +18% | +5% | +5% Fmax @ 1.2V |
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| Chip Density | ? | ? | 1.04x | similar | |
| SRAM Cell Size | 0.0199µm² (-5% vs N5) | 0.021µm² (similar as N5) | ? | ? | |
| Volume Manufacturing |
Late 2022 | H2 2023 | H2 2024 | 2025 | |
While it appears like the unique N3 (aka N3B) could have a comparatively muted lifecycle since Apple has been its solely main buyer, N3E will probably be adopted by a variety of TSMC’s clients, which incorporates lots of the trade’s greatest chip designers.
Since N3P is an optical shrink of N3E, it’s suitable with its predecessor when it comes to IP blocks, course of guidelines, digital design automation (EDA) instruments, and design methodology. As a end result, TSMC expects nearly all of new tape outs to make use of N3P, not N3E or N3. This is logical as N3P supplies larger efficiency effectivity than N3E at a decrease price than N3.
The most vital side of N3P is that it’s on observe to be manufacturing prepared within the second half of this 12 months, so anticipate chip designers to undertake it right away.
“We have also successfully delivered N3P technology,” the TSMC govt stated. “It has handed qualification and yield efficiency is near…
