In what appears to be a significant blunder by the SiPearl PR group, a current go to by a neighborhood French politician resulted within the public Twitter posting in what appears to be like like the ground plan of the corporate’s first-generation server chip challenge “Rhea”.
During a go to of Alexandra Dublanche, a neighborhood Île-de-France politician and vice chairman of financial improvement and different duties for the area, the PR groups had made some photo-op captures of a tour of the workplace. Amongst the revealed photos features a shot of the corporate’s Rhea server chip challenge with some new, till now unreleased particulars of the European Processor Initiative-backed challenge.
Accélérer le développement européen de microprocesseurs à haute efficiency est un enjeu de souveraineté 🇪🇺
C’est le défi auquel s’attaque la pépite technologique @SIPEARL_SAS basée à #MaisonsLaffitte en @iledefrance
La Région sera à ses côtés face à cet enjeu majeur! pic.twitter.com/kcBwghlfsP
— Alexandra Dublanche (@ADublanche) September 8, 2020
In a close-up and up-scaling of the picture, we will see that it’s an in depth floor-plan of the server SoC Rhea, labelled for a goal TSMC 7nm course of.
We can element 72 CPU cores and 68 mesh community L3 cache slices within the ground plan, surrounded by numerous IP whose labels are too small to be legible. SiPearl had beforehand confirmed that the challenge makes use of Arm’s upcoming Neoverse “Zeus” cores which succeed the Neoverse N1 Ares cores which are being utilized in present era Arm server SoC designs similar to Amazon’s Graviton2 or Ampere’s Altra.
Beyond the affirmation of a core-count, we additionally see that the Rhea design sports activities a high-end reminiscence subsystem, with the ground plan labelled as having 4x HBM2E controllers and 4-6 DDR5 controllers. Such a hybrid reminiscence system would enable for very excessive bandwidth to have the ability to feed such numerous cores, whereas nonetheless falling again to common DIMMs to have the ability to scale in reminiscence capability.
The Rhea household of processors is roadmapped to return to market in 2021. The solely curious divergence right here is that SiPearl beforehand said that this was an N6 challenge, while the current Twitter image states it being N7. Given that each processes are design appropriate, it would simply be a current shift within the challenge, or the corporate nonetheless plans to productise it within the N6 node relating to market.
The design’s aggressive reminiscence subsystem with the inclusion of HBM2E factors out that the corporate is aiming for fairly excessive efficiency targets, becoming a member of the ranks of Fujitsu when it comes to designing a CPU with superior HBM reminiscence.
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