This week Samsung Electronics and Synopsys introduced that Samsung has taped out its first cellular system-on-chip on Samsung Foundry’s 3nm gate-all-around (GAA) course of expertise. The announcement, coming from digital design automation Synopsys, additional notes that Samsung used the Synopsys.ai EDA suite to place-n-route the structure and confirm design of the SoC, which in flip enabled greater efficiency.
Samsung’s unnamed high-performance cellular SoC depends on ‘flagship’ general-purpose CPU and GPU architectures in addition to varied IP blocks from Synopsys. SoC designers used Synopsys.ai EDA software program, together with the Synopsys DSO.ai to fine-tune design and maximize yields in addition to Synopsys Fusion Compiler RTL-to-GDSII answer to realize greater efficiency, decrease energy, and optimize space (PPA).
And whereas the information that Samsung has developed a high-performance SoC utilizing the Synopsys.ai suite is necessary, there’s one other, much more necessary dimension to this announcement: which means that Samsung has lastly taped out a sophisticated smartphone utility processor on its cutting-edge 3nm GAAFET course of.
Although Samsung Foundry has been producing chips on its GAA-equipped SF3E (three nm-class, ‘early’ node) course of for nearly two years now, Samsung Electronics has by no means used this expertise for its personal system-on-chips for smartphones or different complicated units. To date, SF3E has been used primarily for cryptocurrency mining chips, presumably because of the inevitable early teething and yield points that include being the business’s first business GAAFET course of.
For now, Samsung is not disclosing what particular course of node is getting used for the SoC; the official Samsung/Synposys announcement solely notes that it is for a GAA course of node. Along with their first-generation 3nm-class SF3E, Samsung Foundry has a significantly extra subtle SF3 manufacturing expertise that provides quite a few enhancements over SF3E, and is due for use for mass manufacturing within the coming quarters. Given the timing of the announcement, the affordable guess is that they are utilizing SF3.
As for Samsung’s tooling partnership with Synopsys, the latter’s instruments are being credited for delivering some vital efficiency enhancements to the chip’s design. In specific, the 2 corporations are crediting these instruments for bettering the chip’s peak clockspeed by 300MHz whereas reducing down on dynamic energy utilization by 10%. To accomplish that, Samsung Electronics’ SoC builders used design partitioning optimization, multi-source clock tree synthesis (MSCTS), and sensible wire optimization to cut back sign interference, together with an easier hierarchical strategy. And by utilizing Synopsys Fusion Compiler, they did all this whereas with the ability to skip weeks of ‘guide’ design work, in keeping with the joint press launch.
“Our longstanding collaboration has delivered leading-edge SoC designs,” stated Kijoon Hong, vice chairman of SLSI at Samsung Electronics. “This is a remarkable milestone to successfully achieve the highest performance, power and area on the most advanced mobile CPU cores and SoC designs in collaboration with Synopsys. Not only have we demonstrated that AI-driven solutions can help us achieve PPA targets for even the most advanced GAA process technologies, but through our partnership we have established an ultra-high-productivity design system that is consistently delivering impressive results.”
