As a part of Samsung’s Q1 earnings announcement, the corporate has outlined a few of its foundry unit’s key plans for the remainder of the yr. The firm has confirmed that it stays on monitor to assembly its objective of beginning mass manufacturing of chips on its SF3 (three nm-class, 2nd Generation) know-how within the second half of the yr. Meanwhile in June, Samsung Foundry will formally unveil its SF2 (2 nm-class) course of know-how, which can supply a mixture of efficiency and effectivity enhancements. Finally, the corporate the corporate is making ready a variation of its four nm-class know-how for integration into stacked 3D designs.
SF2 To Be Unveiled In June
Samsung plans to reveal key particulars about its SF2 fabrication know-how on the VLSI Symposium 2024 on June 19. This would be the firm’s second main course of node based mostly upon gate-all-around (GAA) multi-bridge channel field-effect transistors (MBCFET). Improving over its predecessor, SF2 will characteristic a ‘distinctive epitaxial and integration course of,’ which can give the method node increased efficiency and decrease leakage than conventional FinFET-based nodes (although Samsung is not disclosing the precise node they’re evaluating it to).
Samsung says that SF2 will increase efficiency of slim transistors by 29% for N-type and 46% for P-type, and huge transistors by 11% and 23% respectively. Moreover, it reduces transistor international variation by 26% in comparison with FinFET know-how, and cuts product leakage by roughly 50%. This course of additionally units the stage for future developments in know-how via enhanced design know-how co-optimization (DTCO) collaboration with its clients.
One factor that Samsung has not talked about in context of SF2 is bottom energy supply, so at the very least for the second, there isn’t a indication that Samsung will probably be adopting this next-gen energy routing characteristic for SF2.
Samsung says that the design infrastructure for SF2 – the PDK, EDA instruments, and licensed IP – will probably be finalized within the second quarter of 2024. Once this occurs, Samsung’s chip improvement companions will be capable to start designing merchandise for this manufacturing node. Meanwhile, Samsung is already working with Arm to co-optimize Arm’s Cortex cores for the SF2 course of.
SF3: On Track for 2H 2024
As the primary fab to introduce a GAAFET-based node, Samsung has been on the slicing fringe of chip building. At the identical time, nevertheless, that has additionally meant that they are the primary fab to come across and resolve the inevitable teething points that include such a significant transistor design change. Consequently, whereas Samsung’s first-generation SF3E course of know-how has been in manufacturing for rather less than two years now, the one publicly-disclosed chips made on the method to this point have been comparatively small cryptocurrency mining chips – precisely the sort of pipecleaner elements that do properly on a brand new course of node.
But with that have in hand, Samsung is making ready to maneuver on to creating larger and higher chips with GAAFETs. As a part of their earnings bulletins, the corporate has confirmed that their up to date SF3 node, which was launched final yr, stays on schedule to enter manufacturing within the second half of 2024.
A extra mature product from the get-go, SF3 is being ready for use for constructing bigger processors, together with datacenter merchandise. Compared to its direct predecessor, SF4, SF3 guarantees a 22% efficiency increase on the identical energy and transistor depend, or a 34% decrease energy on the identical frequency and complexity, in addition to a 21% logic space discount. In normal, Samsung pins a whole lot of hopes on this know-how, because it’s this technology of their 3nm-class know-how that’s poised to compete towards TSMC’s N3B and N3E nodes.
SF4: Ready for 3D Stacking
Finally, Samsung can be making ready a variant of…
