ISCA, the International Symposium for Computer Architecture is an IEEE convention that normally we don’t have a tendency to listen to from all that usually within the public. The foremost cause for that is that almost all classes and papers are usually extra academically oriented, and thus usually fairly a bit additional away from the apply of what we see in actual merchandise. This yr, the convention has modified its format in including an business monitor of classes, with displays and papers from numerous firms within the business, protecting precise industrial merchandise on the market within the wild.
Amongst the classes, Samsung’s SARC (Samsung Austin R&D Centre) CPU improvement workforce has introduced a paper titled “Evolution of the Samsung Exynos CPU Architecture”, detailing the workforce’s efforts over its 8-year existence, and introduced some key traits of its customized Arm CPU cores starting from the Exynos M1, to the latest Exynos M5 CPU in addition to the unreleased M6 design.
As a little bit of background, Samsung’s SARC CPU workforce was established in 2011 to develop customized CPU cores that Samsung LSI would then deploy in its Exynos SoCs, starting from the first-generation Exynos 8890 launched in 2015 within the Galaxy S7, up until the latest Exynos 990 with its M5 cores within the Galaxy S20. SARC had accomplished the M6 microarchitecture earlier than the CPU workforce had gotten information of it being disbanded in October of 2019, efficient final December.
The ISCA paper is a results of Samsung’s willingness to publish a few of the improvement workforce’s concepts that had been thought of worthy of preserving within the public, basically representing a high-level burn-through of Eight years of improvement.
From M1 to M6: A constantly morphing CPU µarch
The paper presents a gross overview desk of the microarchitectural variations between Samsung’s customized CPU cores:
The disclosure covers a few of the well-known traits of the design as had been disclosed by Samsung in its preliminary M1 CPU microarchitecture deep dive at HotChips 2016, to the newer M3 deep dive at HotChips 2018. It provides us an perception into the brand new M4 and M5 microarchitectures that we had measured in our S10 and S20 opinions, in addition to a glimpse of what the M6 would have been.
The one key attribute of Samsung’s design was through the years, it was based mostly off the identical blueprint RTL that was began off with the M1 core in 2011, with steady enhancements of the purposeful blocks of the cores through the years. The M3 had been an enormous change within the design, widening the core considerably in a number of points, similar to going from a 4-wide design to a 6-wide mid-core.
The new disclosures that weren’t public earlier than regard the brand new M5 and M6 cores. For the M5, Samsung had made larger adjustments to the cache hierarchy of the cores, similar to changing personal L2 caches with a brand new larger shared cache, in addition to disclosing a change within the L3 construction from a 3-bank design to a 2-bank design with much less latency.
The unreleased M6 core that had been in improvement was seemingly to be an even bigger leap when it comes to the microarchitecture. The SARC workforce right here had ready giant enhancements, similar to doubling the L1 instruction and information caches from 64KB to 128KB – a design selection that’s at the moment solely been applied earlier than by Apple’s CPU cores beginning with the A12.
The L2 is claimed to have been doubled in its bandwidth capabilities to as much as 64B/cycle, and in addition there would have been a rise within the L3 from Three to 4MB.
The M6 would have been an 8-wide decode core, which so far as we all know would have been the widest industrial microarchitecture that we all know of – no less than on the decode aspect of issues.
Interestingly, regardless that the core would have been a lot wider, the integer execution items wouldn’t have modified all…
