One battleground on this planet of FPGAs is the transceiver – the power to herald (or push out) excessive velocity indicators onto an FPGA at low energy. In a world the place FPGAs provide the final word capability in re-programmable logic, having a number of transceivers to herald the bandwidth is a key a part of design. This is why SmartNICs and dense server-to-server interconnect topologies all depend on FPGAs for preliminary deployment and adaptation, earlier than maybe shifting to an ASIC. As a end result, the important thing FPGA firms that play on this house usually have a look at high-speed transceiver adoption and design as a part of the product portfolio.
In latest reminiscence, Xilinx and Altera (now Intel), have been going forwards and backwards, speaking about 26G transceivers, 28G transceivers, 56G/58G, and we got a glimpse into the 116G transceivers that Intel will implement as an possibility for its M-Series 10nm Agilex FPGAs again at Arch Day 2018. The Ethernet primarily based 116G ‘F-Tile’ is a separate chiplet module linked to the central Agilex FPGA by way of an Embedded Multi-Die Interconnect Bridge (EMIB), as it’s constructed on a distinct course of to the primary FPGA.
As a part of Intel’s Architecture Day 2020, the corporate introduced that it’s now engaged on a brand new larger velocity module, rated at 224G. This module is about to assist each 224G in a PAM4 mode (4-bits) and 112G in an NRZ mode (2-bits). This ought to allow future generations of the Ethernet protocol stack, and Intel says it is going to be prepared in late 2021/2022 and can be backwards appropriate with the Agilex hardened 100/200/400 GbE stack. Intel didn’t go into any element about bit-error charges or energy at the moment, however did present a few fancy eye diagrams.
