One of the principle battlegrounds of future modern semiconductor merchandise can be within the packaging expertise: having the ability to combine a number of components of silicon onto the identical package deal with excessive bandwidth and low energy interconnects can be, in accordance with Intel, a technique of extending the efficiency facets of Moore’s Law into the subsequent decade. Intel has three new components to its superior packaging portfolio: EMIB, Foveros, and ODI. At Intel’s Architecture Day 2020, we discovered that Intel’s subsequent technology of FPGA merchandise, constructed on Intel’s personal future 7nm manufacturing course of, will combine EMIB from its present technology in addition to Foveros 3D stacking.
EMIB, or Embedded Multi-Die Interconnect Bridge, is basically a little bit of silicon embedded right into a PCB substrate that enables a silicon die to hook up with it in a really dense means. Two bits of silicon can connect with a single EMIB, permitting a quick and low energy point-to-point interconnect. We have seen EMIB in use with Kaby Lake-G, the Stratix 10 GX 10M FPGAs, and for upcoming variations of Intel’s Xe graphics portfolio, reminiscent of Ponte Vecchio and Xe-HP. Intel has additionally launched a royalty free model of EMIB, known as AIB, which has its personal generation-on-generation improve path to be used within the wider trade.
Foveros is Intel’s die-to-die ‘3D’ stacking expertise that enables two bits of silicon to attach on prime of one another, once more in a high-bandwidth and low energy implementation. Foveros is presently in use in Intel’s Lakefield cell processor, and has been introduced for future merchandise reminiscent of Ponte Vecchio. We now have one other one so as to add to that checklist: FPGAs.
There is not any distinct element about what the subsequent technology FPGAs would have, other than Intel’s 7nm course of and be stacked upon a base die that comprises the HBM IO and DDR connections. I assume that the aim right here is to have a typical base die for a lot of FPGA sizes, after which completely different variants of the 7nm FPGA could possibly be stacked on prime primarily based on buyer wants, or primarily based on productization maybe as a result of yield or price or such. Technically Intel calls any product with each EMIB and Foveros a ‘Co-EMIB’ product, and this falls underneath that naming. One of the brand new components that the 7nm FPGAs could have entry to is a brand new 224G PAM4 transceiver module, which Intel is presently within the means of tuning and validating.
It is unclear precisely when these new 7nm FPGAs can be launched – Intel’s personal slide decks present a roadmap the place the present 10nm Agilex FPGAs are the principle merchandise for 2021/2022, so we’re maybe 2023 or later for these designs. They are far sufficient out that Intel doesn’t have it on the next roadmap:
A phrase on ODI, or Omni-Directional Interconnect. When a chip is constructed with Foveros, the high-power compute chip usually must be on prime for thermal causes, however the energy for that compute chip has to journey via the bottom chip to succeed in the compute one. It additionally signifies that the highest chips are smaller than those beneath. ODI solves this subject, by permitting the highest chip to ‘hang’ over the sting, in a cantilevered vogue, such that the ability connections from the bottom substrate can stand up via on to the compute die. If there are sufficient energy connections, then these connections can be high-bandwidth knowledge connections. This has added advantages in sign integrity, but in addition added issues in manufacturing and structure.
We anticipate ODI for use extra within the small-die area first, maybe in future generations of ‘Lakefield’ sort designs, reasonably than in FPGAs.
