Intel this week has announced its new portfolio of FPGAs designed for small form-factor and/or low-power Internet-of-Things devices, specifically in the fields of automotive, industrial, audio/visual and vision applications. The Cyclone 10 GX and Cyclone 10 LP FPGAs formally belong to a single family of products, but both have different capabilities and were developed for different needs.
The Intel Cyclone 10 GX FPGAs are designed for applications that need relatively high performance (up to 134 GFLOPS, IEEE 754 single-precision) and advanced I/O capabilities. The new FPGAs contain up to 220,000 logic elements, up to 80,330 adaptive logic modules (ALMs) with 8-input look-up tables (LUT), support 10 G transceivers as well as a PCIe 2.0 x4 IP block to connect to CPUs and other devices. Among devices that will use the Cyclone 10 GX FPGAs Intel names industrial machine vision, smart city surveillance, video streaming, robotics, machine tools and other devices. The 10 GX family is made on TSMC’s 20nmSoC planar process, in line with what we perhaps expect as Intel is working through Altera roadmaps set before the acquisition.
By contrast, the Intel Cyclone 10 LP FPGAs are aimed at low-power/low-cost applications, such as sensor fusion, motor controls, interfacing, I/O expansion for CPUs and so on. For example, if an application needs to combine data from multiple sensors, the Cyclone 10 LP will do the job, but the actual processing will be performed by something more powerful. The FPGAs contain 6,000 – 120,000 logic elements, DSP blocks (up to 288 18×18 multipliers), integrated PLLs, 65 – 230 LVDS channels and so on.
Both families of the Cyclone 10 FPGAs are compliant with the IEC 61508 machinery directive safety standard (in fact, Intel says that it is the first FPGA vendor to obtain the appropriate device and tool qualification), which in case of a chip probably indicates its reliability during continuous operation.
| Intel Cyclone 10 FPGAs | ||||
| Cyclone 10 GX | Cyclone 10 LP | |||
| Logic elements (LEs) | 85,000 – 220,000 | 6,000 – 120,000 | ||
| Adaptive logic modules (ALMs) | 31,000 – 80,330 | – | ||
| ALM registers | 124,000 – 321,320 | – | ||
| Variable-precision DSP blocks | 84 – 192 | – | ||
| 18 x 19 multipliers | 168 – 384 | – | ||
| 18 x 18 multipliers | – | 15 – 288 | ||
| Peak fixed-point peformance (GMACS) | 151 – 346 | – | ||
| Peak floating-point performance (GFLOPS) | 59 – 134 | – | ||
| Voltage | Core voltage: 0.9 V I/O Voltage: Various |
1.0 and 1.2 V | ||
| Process Technology | 20 nm (TSMC CLN20SOC) | unknown | ||
| I/O | ||||
| Global clock networks | 32 | 10 – 20 | ||
| Maximum user I/O pins | 192 – 284 | 176 – 525 | ||
| Maximum LVDS pairs 1.4 Gbps (RX or TX) | 72 – 118 | |||
| Maximum LVDS channels | – | 65 – 230 | ||
| Maximum transceiver count (10.3 Gbps) | 4 – 12 | – | ||
| Maximum 3V I/O pins | 48 | – | ||
| PCIe 2.0 x4 hard IP blocks | 1 | – | ||
| Memory devices supported | DDR3, DDR3L, LPDDR3 | – | ||
| Packaging | ||||
| E144 pin | – | 22 x 22 mm, 0.5 mm pitch | ||
| M164 pin | – | 8 x 8 mm, 0.5 mm pitch | ||
| U256 pin | – | 14 x 14 mm, 0.8 mm pitch | ||
| U484 pin | 19 x 19 mm, 0.8 mm pitch | |||
| F484 pin | – | 23 x 23 mm, 1.0 mm pitch | ||
| F672 pin | 27 x 27 mm, 1.0 mm pitch | |||
| F780 pin | 29 x 29 mm, 1.0 mm pitch | |||
Intel’s Cyclone 10-series FPGAs, as well as evaluation kits and boards on their base, will be available in the second half of 2017. In addition to hardware, Intel also plans to release its Quartus programming software that supports the new FPGAs.
Related Reading:
- Intel to Acquire FPGA-Specialist Altera for $16.7 Billion
- Xilinx Launches Cost-Optimized Portfolio: New Spartan, Artix and Zynq Solutions
- Computex 2016: Intel Keynote Live Blog at 2pm TPE (2am EDT)
