Today we posted a information article about SK hynix’s new DDR5 reminiscence modules for purchasers – 64 GB registered modules operating at DDR5-4800, aimed on the preview techniques that the large hyperscalers begin enjoying with 12-18 months earlier than anybody else will get entry to them. It is fascinating to notice that SK Hynix didn’t publish any sub-timing details about these modules, and as we glance via the bulletins made by the foremost reminiscence producers, one widespread theme has been a scarcity of element about sub-timings. Today can current info throughout the complete vary of DDR5 specs.
When discussing reminiscence, there are just a few metrics to think about:
- Type, e.g. DDR4, DDR5
- Capacity
- Power consumption / voltage
- Bandwidth
- Latency
- Price
- Persistence
When constructing a platform, quite a lot of these elements all come into play – a system that implements oil and fuel simulations would possibly require terabytes of reminiscence, no matter energy, of for smaller installations worth is likely to be the foremost concern. For specialist purposes, persistent reminiscence is likely to be a spotlight, or a mix of bandwidth/latency can be key to driving efficiency.
In order for all these corporations that construct reminiscence and techniques to work collectively, a set of requirements are developed by a consortium of all events – that is known as JEDEC. JEDEC creates the requirements to make sure help for all compliant techniques.
Users who’re aware of JEDEC specs will word that shopper grade reminiscence is commonly specified sooner than what JEDEC lists – it is a function by which processors that may help sooner reminiscence, when paired with reminiscence certified to be sooner than JEDEC, could be paired collectively. This is why we see reminiscence kits all the best way as much as DDR4-5000 out there immediately that solely work with just a few choose techniques.
Read AnandTech’s Corsair DDR4-5000 Vengeance LPX Review
Super-Binned, Super Exclusive
For DDR4, JEDEC helps requirements starting from DDR4-1600 as much as DDR4-3200. From the information fee, a peak switch fee could be calculated (12.eight GB/s per channel for DDR4-1600, 25.6 GB/s per channel for DDR4-3200), nonetheless the latency requires extra info. The typical sub-timings provided with reminiscence are:
- CAS: Column Address Strobe: the time between sending a column handle and the response
- tRCD: Row to Column Delay: clock cycles to load a column when new row is opened
- tRP: Row Precharge Time: clock cycles to load knowledge when mistaken row is open
- tRAS: Row Active Time: minimal time between row lively and precharge
These are sometimes reported as CAS-tRCD-tRP with tRAS typically added on. This implies that in JEDEC’s DDR4 specification, the bottom DDR4-3200 metric permits for a 24-24-24 set of sub-timings. For latency calculations, we’d like each the information fee (3200 MT/s) and the CAS (24 clocks) to calculate the CAS by way of nanoseconds, the true world latency (on this case, 15 nanoseconds).
The mixture of knowledge fee and CAS Latency has been used to match single entry latency numbers for reminiscence through the years. Moving from the early iterations of DRAM, each knowledge entry charges and single entry latencies have improved. However just lately, as a consequence of bodily limitations, whereas knowledge fee has been growing, entry latency has been roughly constant.
| Memory and Bandwidth, as much as DDR4 | |||||
| AnandTech | Data Rate MT/s |
Bandwidth GB/s |
CAS (clk) |
Latency (ns) |
|
| SDR | |||||
| SDR | 100 | 100 | 0.80 | 3 | 24.00 |
| 133 | 133 | 1.07 | 3 | 22.50 | |
| DDR | |||||
| DDR | 200 | 200 | 1.60 | 2 | 20.00 |
| 333 | 333 | 2.67 | 2.5 | 15.00 | |
| 400 | 400 | 3.20 | 3 | 15.00 | |
| DDR 2 | |||||
| DDR2 | 400 | 400 | 3.20 | 5 | 25.00 |
| 667 | 667 | 5.33 | 5 | 15.00 | |
| 800 | 800 | 6.40 | 6 | 15.00 | |
| Source
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