Imec and ASML have introduced that the 2 firms have printed the primary logic and DRAM patterns utilizing ASML’s experimental Twinscan EXE:5000 EUV lithography device, the trade’s first High-NA EUV scanner. The lithography system achieved decision that’s adequate for 1.4nm-class course of know-how with only one publicity, which confirms the capabilities of the system and that improvement of the High-NA ecosystem stays on-track to be used in business chip manufacturing later this decade.
“The results confirm the long-predicted resolution capability of High NA EUV lithography, targeting sub 20nm pitch metal layers in one single exposure,” stated Luc Van den hove, president and CEO of imec. “High NA EUV will therefore be highly instrumental to continue the dimensional scaling of logic and memory technologies, one of the key pillars to push the roadmaps deep into the ‘angstrom era’. These early demonstrations were only possible thanks to the set-up of the joint ASML-imec lab allowing our partners to accelerate the introduction of High NA lithography into manufacturing.”
The profitable check printing comes after ASML and Imec have spent the final a number of months laying the groundwork for the check. Besides the years required to construct the advanced scanner itself, engineers from ASML, Imec, and their companions wanted to develop newer photoresists, underlayers, and reticles. Then they needed to take an current manufacturing node and tune it for High-NA EUV instruments, together with doing optical proximity correction (OPC) and tuning etching processes.
The fruits of those efforts was that, utilizing ASML’s pre-production Twinscan EXE:5000 system, Imec was capable of efficiently sample random logic buildings with 9.5nm dense steel strains, which corresponds to a 19nm pitch and sub-20nm tip-to-tip dimensions. Similarly, Imec additionally set new excessive marks in function density in different respects, together with patterning of 2D options at a 22nm pitch, and printing random vias with a 30nm center-to-center distance, demonstrating excessive sample constancy and demanding dimension uniformity.
The total result’s that Imec’s experiments have confirmed that ASML’s High-NA scanner is delivering on its meant capabilities, printing options at a wonderful sufficient decision for fabricating logic on a 1.4nm-class course of know-how – and all with a single publicity. The latter is maybe crucial facet of this tooling, because the excessive value and complexity of the High-NA device itself (stated to be round $400 million) is meant to be offset by having the ability to return to single-patterning, which permits for greater device productiveness and fewer steps total.
Imec hasn’t simply been printing logic buildings, both; the group efficiently patterned DRAM designs as properly, printing each a storage node touchdown pad alongside the bit line periphery for reminiscence in a single publicity. As with their logic assessments, this might enable DRAM designs to be printed in only one publicity, decreasing cycle occasions and finally prices.
9,5nm random logic construction (19nm pitch) after sample switch
“We are thrilled to demonstrate the world’s first High NA-enabled logic and memory patterning in the joint ASML-imec lab as an initial validation of industry applications,” stated Steven Scheer, senior vice chairman of compute applied sciences & techniques/compute system scaling at imec. “The results showcase the unique potential for High NA EUV to enable single-print imaging of aggressively-scaled 2D features, improving design flexibility as well as reducing patterning cost and complexity. Looking ahead, we expect to provide valuable insights to our patterning ecosystem partners, supporting them in further maturing High NA EUV specific materials and equipment.”
