The CXL consortium has had a daily presence at FMS (which rechristened itself from ‘Flash Memory Summit’ to the ‘Future of Memory and Storage’ this yr). Back at FMS 2022, the corporate had introduced v3.Zero of the CXL specs. This was adopted by CXL 3.1’s introduction at Supercomputing 2023. Having began off as a bunch to system interconnect normal, it had slowly subsumed different competing requirements reminiscent of OpenCAPI and Gen-Z. As a consequence, the specs began to embody all kinds of use-cases by constructing a protocol on prime of the the ever-present PCIe growth bus. The CXL consortium includes of heavyweights reminiscent of AMD and Intel, in addition to numerous startup firms trying to play in numerous segments on the system aspect. At FMS 2024, CXL had a main place within the sales space demos of many distributors.
The migration of server platforms from DDR4 to DDR5, together with the rise of workloads demanding giant RAM capability (however not significantly delicate to both reminiscence bandwidth or latency), has opened up reminiscence growth modules as one of many first set of broadly accessible CXL gadgets. Over the final couple of years, we now have had product bulletins from Samsung and Micron on this space.
SK hynix CMM-DDR5 CXL Memory Module and HMSDK
At FMS 2024, SK hynix was displaying off their DDR5-based CMM-DDR5 CXL reminiscence module with a 128 GB capability. The firm was additionally detailing their related Heterogeneous Memory Software Development Kit (HMSDK) – a set of libraries and instruments at each the kernel and consumer ranges aimed toward growing the convenience of use of CXL reminiscence. This is achieved partially by contemplating the reminiscence pyramid / hierarchy and relocating the info between the server’s primary reminiscence (DRAM) and the CXL system based mostly on utilization frequency.
The CMM-DDR5 CXL reminiscence module comes within the SDFF form-factor (E3.S 2T) with a PCIe 3.Zero x8 host interface. The inner reminiscence is predicated on 1α know-how DRAM, and the system guarantees DDR5-class bandwidth and latency inside a single NUMA hop. As these reminiscence modules are meant for use in datacenters and enterprises, the firmware contains options for RAS (reliability, availability, and serviceability) together with safe boot and different administration options.
SK hynix was additionally demonstrating Niagara 2.0 – a {hardware} resolution (at present based mostly on FPGAs) to allow reminiscence pooling and sharing – i.e, connecting a number of CXL reminiscences to permit completely different hosts (CPUs and GPUs) to optimally share their capability. The earlier model solely allowed capability sharing, however the newest model allows sharing of information additionally. SK hynix had introduced these options on the CXL DevCon 2024 earlier this yr, however some progress appears to have been made in finalizing the specs of the CMM-DDR5 at FMS 2024.
Microchip and Micron Demonstrate CZ120 CXL Memory Expansion Module
Micron had unveiled the CZ120 CXL Memory Expansion Module final yr based mostly on the Microchip SMC 2000 sequence CXL reminiscence controller. At FMS 2024, Micron and Microchip had an illustration of the module on a Granite Rapids server.
Additional insights into the SMC 2000 controller have been additionally supplied.
The CXL reminiscence controller additionally incorporates DRAM die failure dealing with, and Microchip additionally supplies diagnostics and debug instruments to investigate failed modules. The reminiscence controller additionally helps ECC, which types a part of the enterprise class RAS function set of the SMC 2000 sequence. Its flexibility ensures that SMC 2000-based CXL reminiscence modules utilizing DDR4 can complement the principle DDR5 DRAM in servers that assist solely the latter.
Marvell Announces Structera CXL Product Line
A couple of days previous to the beginning of FMS 2024, Marvell had introduced a brand new CXL product line below the Structera tag. At FMS 2024, we had an opportunity to debate…
