“Datacenter architectures continue to evolve rapidly to support the growing demands of emerging workloads for Artificial Intelligence and Machine Learning, with CXL technology keeping pace to meet the performance and latency demands,” mentioned Barry McAuliffe, president, CXL Consortium. “Designed with breakthrough performance and easy adoption as guiding principles, the CXL 2.0 specification is a significant achievement from our dedicated technical work group members.”
Key Highlights of the CXL 2.0 Specification:
- Adds assist for switching to allow machine fan-out, reminiscence scaling, enlargement and the migration of assets.
- Includes reminiscence pooling assist to maximise reminiscence utilization, limiting or eliminating the necessity to overprovision reminiscence.
- Introduces standardized cloth supervisor specification for stock and useful resource allocation to allow simpler adoption and administration of CXL-based swap and cloth options.
- Provides standardized administration of the persistent reminiscence interface and permits simultaneous operation alongside DDR, releasing up DDR for different makes use of.
- Introduces managed hot-plug assist to take a CXL machine on-line or offline from the system.
- Adds link-level Integrity and Data Encryption (CXL IDE) to supply confidentiality, integrity and replay safety for information transiting the CXL hyperlink.
- Supports all kinds of {industry} interconnect kind components and standardized administration interfaces to ease implementation.
- Includes Compliance and Interoperability specs and in-system testing to allow a sturdy and interoperable multi-vendor ecosystem.
“The CXL Consortium has moved with breathtaking speed to deliver its second generation CXL 2.0 spec, even before products incorporating the first generation CXL 1.0 and 1.1 specs have reached the market,” noticed Nathan Brookwood, Research Fellow at Insight 64. “The new 2.0 features, including switching, memory pooling and persistent memory support pave the way for fully disaggregated systems in which pools of accelerators, DRAM and persistent memory storage can be dynamically connected to any one of 16 host servers to meet application demands. These features will enable system designers to invent entirely new types of systems that architects could only dream about just a few years ago.”
The CXL 2.Zero specification is on the market for public obtain right here.
