The DDR5 standard has not been finalized by JEDEC, but that is expected sometime this summer. Cadence created a test chip containing next-generation memory interface IP based on the discussions of what is likely to be in DDR5, and Micron produced the prototype DRAM chips.
The test chip was fabricated in TSMC’s 7nm process, and contains both the controller and PHY. The two chips work together successfully achieving 4400 megatransfers per second, 37.5% faster than the fastest commercially available DDR4 memory. As far as we can tell, this is the first demonstration of DDR5 IP working with memory chips, as reportted on the Cadence blog.
DDR5 is mostly a capacity solution, more than performance. As die get bigger, they get slower, due to all sorts of laws of physics. As you start building a 16Gb die in 1X memory technology, the distances start to get really long, which changes a lot of core timing parameters for the worse. Then the memory can’t keep up with the CPU and so has to be overdesigned, making it bigger still, and so on. But everyone wants more memory in each server, for bigger datasets, bigger databases, bigger netlists, and so on. Cloud companies charge people for the memory in their instances and so there is a direct line from memory capacity to revenue. The DDR5 standard is aimed at making 16Gb die easier and to make vertical stacking easier. The speed of the core is unchanged, but the I/O is higher speed.
DDR4 today is not up to its maximum speed. Mainstream parts today are 2400 megatransfers per second. The high end is 2667 (for example, look at what you get if you buy a Dell server). That will become mainstream this year, so we are still a couple of years from DDR4 reaching its maximum of 3200 megatransfers per second. DDR5 is expected to be 4400 megatransfers per second at first, which is what the Cadence test chip achieved. 6400 is the maximum but it will be many years before anyone gets there. As Marc kept emphasizing, DDR5 is more about capacity than performance. Memories “don’t get faster very fast.”
DDR5 Summary (not final)
- supply voltage will drop from 1.2V for DDR4 to 1.1V for DDR5
- data rates will run up to 6.4 Gbps eventually, 4.4Gbps initially
- on-die termination (pulled-up VDDQ) will be available for address buses, not just data buses
What’s Next?
Cadence plans to be first again with IP for LPDDR5 and future generations of other memory standards such as HBM. I’m sure I’ll be covering them when we are ready to announce.
