Today, Apple has unveiled their brand-new MacE-book line-up. This isn’t an unusual launch – if something, the transfer that Apple is making as we speak is one thing that hasn’t occurred in 15 years: The begin of a CPU structure transition throughout their entire shopper Mac line-up.
Thanks to the corporate’s vertical integration throughout {hardware} and software program, this can be a monumental change that no person however Apple can so swiftly usher in. The final time Apple ventured into such an endeavor in 2006, the corporate had ditched IBM’s PowerPC ISA and processors in favor of Intel x86 designs. Today, Intel is being ditched in favor of the corporate’s personal in-house processors and CPU microarchitectures, constructed upon the Arm ISA.
The new processor is known as the Apple M1, the corporate’s first SoC designed with Macs in thoughts. With 4 massive efficiency cores, 4 effectivity cores, and an 8-GPU core GPU, it options 16 billion transistors on a 5nm course of node. Apple’s is beginning a brand new SoC naming scheme for this new household of processors, however a minimum of on paper it seems to be quite a bit like an A14X.
Today’s occasion contained a ton of recent official bulletins, but in addition was missing (in typical Apple trend) intimately. Today, we’re going to be dissecting the brand new Apple M1 information, in addition to doing a microarchitectural deep dive primarily based on the already-released Apple A14 SoC.
The Apple M1 SoC: An A14X for Macs
The new Apple M1 is absolutely the beginning of a brand new main journey for Apple. During Apple’s presentation the corporate didn’t actually disclose a lot in the best way of particulars for the design, nevertheless there was one slide that instructed us quite a bit concerning the chip’s packaging and structure:
This packaging fashion with DRAM embedded inside the natural packaging is not new for Apple; they have been utilizing it because the A12. However it is one thing that is solely sparingly used. When it involves higher-end chips, Apple likes to make use of this sort of packaging as an alternative of your standard smartphone POP (package deal on package deal) as a result of these chips are designed with larger TDPs in thoughts. So protecting the DRAM off to the facet of the compute die slightly than on prime of it helps to make sure that these chips can nonetheless be effectively cooled.
What this additionally means is that we’re virtually actually a 128-bit DRAM bus on the brand new chip, very like that of earlier technology A-X chips.
On the exact same slide, Apple additionally appears to have used an precise die shot of the brand new M1 chip. It completely matches Apple’s described traits of the chip, and it seems to be seems to be like an actual {photograph} of the die. Cue what’s in all probability the quickest die annotation I’ve ever made:
We can see the M1’s 4 Firestorm high-performance CPU cores on the left facet. Notice the massive quantity of cache – the 12MB cache was one of many shock reveals of the occasion, because the A14 nonetheless solely featured 8MB of L2 cache. The new cache right here seems to be to be portioned into three bigger blocks, which is smart given Apple’s transition from 8MB to 12MB for this new configuration, it’s in any case now being utilized by Four cores as an alternative of two.
Meanwhile the 4 Icestorm effectivity cores are discovered close to the middle of the SoC, above which we discover the SoC’s system stage cache, which is shared throughout all IP blocks.
Finally, the 8-core GPU takes up a big quantity of die house and is discovered within the higher a part of this die shot.
What’s most attention-grabbing concerning the M1 right here is the way it compares to different CPU designs by Intel and AMD. All the aforementioned blocks nonetheless solely cowl up a part of the entire die, with a big quantity of auxiliary IP. Apple made point out that the M1 is a real SoC, together with the performance of what beforehand was a number of discrete chips within Mac laptops, akin to I/O controllers and Apple’s SSD and safety…
