TSMC has licensed Ansys’ options for its SoIC (system-on-integrated chips) 3D chip-stacking expertise, in accordance with Ansys, an engineering simulation software program supplier.
Ansys’ multiphysics options for TSMC’s SoIC allow multi-die co-simulation and co-analysis for extraction, energy and sign integrity evaluation, energy and sign electromigration evaluation, and thermal and thermal-induced stress evaluation. In addition, TSMC has validated the reference circulate for the most recent CoWoS (chip-on-wafer-on-substrate) packaging expertise utilizing Ansys’ RedHawk, RedHawk-CTA, CMA and CSM, and their corresponding chip fashions for system stage evaluation.
“We’re pleased with the result of our collaboration with Ansys in delivery of TSMC-SoIC technology reference flow, which empowers customers to address growing performance, reliability and power demands for cloud and data center applications,” stated Suk Lee, senior director of design infrastructure administration for TSMC, in a press release issued by Ansys. “The collaborative efforts combining Ansys’ comprehensive chip-package co-analysis solutions with TSMC SoIC advanced chip stacking technology address complex multiphysics challenges in 3D-IC packaging technologies.”
TSMC’s SoIC is a sophisticated interconnect expertise for multi-die stacking on system-level integration utilizing through-silicon through (TSV) and chip-on-wafer bonding course of enabling clients with higher energy effectivity and efficiency for extremely complicated and demanding cloud and information middle functions.
